Webinar on high-level synthesis (HLS) for high-performance digitizers

Webinar on high-level synthesis (HLS) for high-performance digitizers

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Learn the basics of how HLS helps simplify FPGA firmware development for high-performance digitizers

Date: Tuesday, September 27, 2022

Time: 10 AM PDT | 1 PM EDT

Duration: 30 minutes

Learn about digitizer basics

Join Teledyne SP Devices for an introductory webinar on HLS in the context of high-performance digitizers.

Topics covered in this webinar:

  • Benefits of onboard FPGA signal processing
  • FPGA architecture and development basics
  • Programming languages and development tools
  • Application areas and signal processing examples

Who should attend? Developers that want to learn more about the possibilities and benefits of onboard digital signal processing in high-performance digitizers.

What attendees will learn? An introduction to FPGA development for high-performance digitizers.

Presenter: Thomas Elter, Senior Field Applications Engineer

Register below to attend the webinar

Jennifer R. Kelley

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